* Qualcomm MSM VIDC

Required properties:
- compatible : one of:
	- "qcom,msm-vidc"
- qcom,hfi : supported Host-Firmware Interface, one of:
	- "venus"
	- "q6"
- qcom,max-hw-load: The maximum load the hardware can support expressed in units
  of macroblocks per second. The load is a reflection of hardware capability
  rather than a performance guarantee. Performance is guaranteed only up to
  advertised capability of the chipset.

Optional properties:
- reg : offset and length of the register set for the device.
- interrupts : should contain the vidc interrupt.
- qcom,load-freq-tbl : load (in macroblocks/sec) and corresponding vcodec
  clock required along with codec's config (same as qcom,bus-configs mentioned below)
  for optimal performance in descending order.
- qcom,reg-presets : list of offset-value pairs for registers to be written.
  The offsets are from the base offset specified in 'reg'. This is mainly
  used for QoS, VBIF, etc. presets for video.
- qcom,qdss-presets : list of physical address and memory allocation size pairs.
  when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be
  written to QDSS memory.
- qcom,msm-bus-clients : list of bus clients/consumer each listed as a node.
  The format of the node should follow the layout specified by the bus provider
  for bus consumers at Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
  In addition to the properties specified by the bus provider client also needs
	- qcom,bus-passive: A bool indicating the bus is "not active".  Active
	  buses are defined as buses that are scaled according to hardware load.
	  Passive buses are not scaled by load and are typically just "turned on"
	  to keep certain clocks (that aren't directly controllable by the driver)
	  high.
        - qcom,bus-configs: A bitmap that describes the configuration of the
          bus. The bitmaps are as follows:
          supports mvc encoder = 0x00000001
          supports mvc decoder = 0x00000003
          supports h264 encoder = 0x00000004
          supports h264 decoder = 0x0000000c
          supports h263 encoder = 0x00000010
          supports h263 decoder = 0x00000030
          supports mpeg1 encoder = 0x00000040
          supports mpeg1 decoder = 0x000000c0
          supports mpeg2 encoder = 0x00000100
          supports mpeg2 decoder = 0x00000300
          supports mpeg4 encoder = 0x00000400
          supports mpeg4 decoder = 0x00000c00
          supports divx_311 encoder = 0x00001000
          supports divx_311 decoder = 0x00003000
          supports divx encoder = 0x00004000
          supports divx decoder = 0x0000c000
          supports vc1 encoder = 0x00010000
          supports vc1 decoder = 0x00030000
          supports spark encoder = 0x00040000
          supports spark decoder = 0x000c0000
          supports vp6 encoder = 0x00100000
          supports vp6 decoder = 0x00300000
          supports vp7 encoder = 0x00400000
          supports vp7 decoder = 0x00c00000
          supports vp8 encoder = 0x01000000
          supports vp8 decoder = 0x03000000
          supports hevc encoder = 0x04000000
          supports hevc decoder = 0x0c000000
          supports hevc_hybrid encoder = 0x10000000
          supports hevc_hybrid decoder = 0x30000000
- qcom,ocmem-size: ocmem size required by hardware for optimum performance.
  If ocmem is not present then there is no need to specify this property.
- qcom,vidc-iommu-domains: node containing individual domain nodes, each with:
        - a unique domain name for the domain node (e.g vidc,domain-ns)
        - qcom,vidc-domain-phandle: phandle for the domain as defined in
          <target>-iommu-domains.dtsi (e.g msm8974-v1-iommu-domains.dtsi)
        - qcom,vidc-partition-buffer-types: bitmap of buffer types that can
          be mapped into each IOMMU domain partition.  There must be exactly
          one buffer bitmap per partition in the domain, with order of the
          bitmaps to be the same as the order of the respective partitions.
        - Buffer types are defined as the following:
          input = 0x1
          output = 0x2
          output2 = 0x4
          extradata input = 0x8
          extradata output = 0x10
          extradata output2 = 0x20
          internal scratch = 0x40
          internal scratch1 = 0x80
          internal scratch2 = 0x100
          internal persist = 0x200
          internal persist1 = 0x400
          internal cmd queue = 0x800
- *-supply: A phandle pointing to the appropriate regulator. Number of
  regulators vary across targets.
- clock-names: an array of clocks that the driver is supposed to be
  manipulating. The clocks names here correspond to the clock names used in
  clk_get(<name>).
- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index
  of the bitmap corresponds to the clock at the same index in qcom,clock-names.
  The bitmaps describes the actions that the device needs to take regarding the
  clock (i.e. scale it based on load).

  The bitmap is defined as:
  scalable = 0x1 (if the driver should vary the clock's frequency based on load)
  gate-able = 0x2 (if the driver should disable the clock if no load)
- qcom,sw-power-collapse = A bool indicating if video hardware core can be
  power collapsed in idle state.
- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load
  the fw.
- qcom,use-dynamic-bw-update = A bool indicating whether dynamic bandwidth
  update request should be sent to msm bus or not.
- qcom,fw-bias = The address at which venus fw is loaded (manually).
- qcom,enable-idle-indicator = A bool to enable video hardware to generate
  idle message when it is in idle state.
- qcom,pm-qos-latency-us = The latency used to vote for QOS power manager. This
value is typically max(latencies of every cluster at all power levels) + 1

Example:


	qcom,vidc@fdc00000 {
		compatible = "qcom,msm-vidc";
		reg = <0xfdc00000 0xff000>;
		interrupts = <0 44 0>;
		venus-supply = <&gdsc>;
		venus-core0-supply = <&gdsc1>;
		venus-core1-supply = <&gdsc2>;
		qcom,load-freq-tbl =
			<489600 266670000 0x030fcfff>, /* Legacy decoder 1080p 60fps  */
			<108000 133330000 0x030fcfff>, /* Legacy decoder 720p 30fps   */
			<108000 200000000 0x01000414>, /* Legacy encoder 720p 30fps   */
			<72000 133330000 0x0c000000>, /* HEVC decoder VGA 60fps   */
			<36000 133330000 0x0c000000>, /* HEVC VGA 30 fps  */
			<36000 133330000 0x01000414>; /* Legacy encoder VGA 30 fps   */
		qcom,ocmem-size = <4096>;
		qcom,hfi = "venus";
		qcom,reg-presets = <0x80004 0x1>,
			<0x80178 0x00001FFF>;
		qcom,qdss-presets = <0xFC307000 0x1000>,
			<0xFC322000 0x1000>;
		qcom,max-hw-load = <1224450>; /* 4k @ 30 + 1080p @ 30*/
		clock-names = "foo_clk", "bar_clk", "baz_clk";
		qcom,clock-configs = <0x3 0x1 0x0>;
		qcom,sw-power-collapse;
		qcom,enable-idle-indicator;
		qcom,msm-bus-clients {
			qcom,msm-bus-client@0 {
				qcom,msm-bus,name = "venc-ddr";
				qcom,msm-bus,num-cases = <2>;
				qcom,msm-bus,active-only = <0>;
				qcom,msm-bus,num-paths = <1>;
				qcom,msm-bus,vectors-KBps =
					<63 512 0 0>,
					<63 512 60000 302000>;
				qcom,bus-configs = <0x2>;
			};
			qcom,msm-bus-client@1 {
				qcom,msm-bus,name = "vdec-ddr";
				qcom,msm-bus,num-cases = <2>;
				qcom,msm-bus,active-only = <0>;
				qcom,msm-bus,num-paths = <1>;
				qcom,msm-bus,vectors-KBps =
					<63 512 0 0>,
					<63 512 104000 303000>;
				qcom,bus-configs = <0xf>;
				qcom,bus-passive;
			};
		};
		qcom,vidc-iommu-domains {
			qcom,domain-ns {
				qcom,vidc-domain-phandle = <&venus_domain_ns>;
				qcom,vidc-partition-buffer-types = <0x7ff>,
							<0x800>;
			};

			qcom,domain-cp {
				qcom,vidc-domain-phandle = <&venus_domain_cp>;
				qcom,vidc-partition-buffer-types = <0x6>,
							<0x7c1>;
			};
		};
		qcom,use-non-secure-pil;
		qcom,use_dynamic_bw_update;
		qcom,fw-bias = <0xe000000>;
	};
