* MSM PM

PM is the low power management device for MSM (Snapdragon class) chipsets.
This device sets up different components to do low power modes and registers with
the kernel to be notified of idle and suspend states and when called, follows
through the set of instructions in putting the application cores to the lowest
power mode possible.
The PC debug counter reserves 16 registers in the IMEM memory space which maintains
a count on the state of power collapse on each core. This count will be useful to
debug the power collapse state on each core.

The required properties for PM are:

- compatible: "qcom,pm"

The optional properties are:

- reg: physical IMEM address reserved for PC counters and the size
- qcom,use-sync-timer: Indicates whether the target uses the synchronized QTimer.
- qcom,saw-turns-off-pll: Version of SAW2.1 or can turn off the HFPLL, when
	doing power collapse and so the core need to switch to Global PLL before
	PC.
- qcom,synced-clocks: Indicates that all cpus running off a single clock source and to
	instantiate the necessary clock source.
- qcom,pc-resets-timer: Indicates that the timer gets reset during power collapse.
- qcom,tz-flushes-cache: Indicates that TZ flushes all of the cache during
power collapse. MSM PM can decide to not perform cache flush operations to
reduce latency associated with L2 PC.

Example:

qcom,pm@fe800664 {
		compatible = "qcom,pm";
		reg = <0xfe800664 0x40>;
		qcom,use-sync-timer;
	};
